A video game system includes an audio digital signal processor, a main memory and an audio memory separate from the main memory and storing audio-related data for processing by the audio digital signal processor. Memory access circuitry reads non-audio-related data stored on a mass storage device and writes the non-audio-related data to the audio memory. The non-audio-related data is later read from the audio memory and written to the main memory.

Current U.S. Class:	711/137; 712/207
Intern'l Class:	G06F 012/00
Field of Search:	711/137 709/203,231 345/430,520,522 712/205-207

    Bits      Name              Type  Reset Description
    15 . . . 1                   R     0x0   Reserved
     0        DMA request mask  R/W   0x0   0: DMA request ARAM
                                            is unmasked
                                            1: DMA request ARAM
                                            is masked

    Bits      Name        Type  Reset     Description
                DSMAH: DSp dma Main memory Address
                      High DSPaddress 0xFFCE
    15 . . . 10 6 bits of its R     0x0       This register is used to
              MSBs                        specify DSP DMA main
                                          memory starting/current
                                          address from bit 31 to
                                          bit 26, and
                                          always 0
     9 . . . 0 Main        R/W   undefined This register is used to
              memory                      specify DSP DMA main
              address                     memory starting/current
              high word                   address from bit 25 to
                                          bit 16
                DSMAL: DSp dma Main memory Address
                      Low DSPaddress 0xFFCF
    15 . . . 2 Main        R/W   undefined This register is used to
              memory                      specify DSP DMA main
              address                     memory starting/current
                                          address from bit 15
                                          to bit 2
    1,0       2 bits of its R     0x0       The main memory address
              LSBs                        of this DMA should be
                                          located at 4 byte
                                          boundary
     DSPA: DSp dma dsP memory Address High DSPaddress 0xFFCD
    15 . . . 1 DSP         R/W   undefined This register is used to
              memory                      specify DSP memory
              address                     starting/current address
                                          from bit 15 to bit 1
    0         1 bit of its R     0x0       The DSP memory
              LSBs                        address should be located
                                          at 2 word boundary
           DSBL: DSp dma Block Length DSPaddress 0xFFCB
    15 . . . 2 block       R/W   0x0       This register is used to specify DSP
              length                      DMA transfer length from bit 15 to
     bit
                                          2
    1,0       2 bit of its R     0x0       The transfer length is a multiple of
     4
              LSBs                        bytes
         DSCR: DSp dma Control Register DSPaddress 0xFFC9
    15 . . . 3             R     0x0       reserved
    2         DSP DMA     R     0x0       Block length counter not yet zero,
              busy                        DMA is still busy
    1         DSP         R/W   0x0       DMA involved DSP memory
              source/                     0: DSP data memory
              destination                 1: DSP instruction memory
    0         transfer    R/W   0x0       0: from main memory to DSP memory
              direction                   1: from DSP memory to main memory

    Bits      Name          Type  Reset Description
           ACCAH: Accelerator aram Current Address High
                        DSP Address:0xFFD8
    15        Direction     R/W   0x0   0: accelerator read ARAM
                                        1: accelerator write ARAM
    14 . . . 11               R     0x0   Reserved
    10 . . . 0 Current address R/W   0x0   Bit 26 to bit 16 of ARAM
              high-word                 current address
             ACCAL: Accelerator aram Current Address
                      Low DSP Address:0xFFD9
    15 . . . 0 Current address R/W   0x0   Bit 15 to Bit 0 of ARAM
              low-word                  current address
              ACEAH: Accelerator aram Ending Address
                     High DSP Address:0xFFD6
    15 . . . 11               R     0x0   Reserved
    10 . . . 0 Ending address R/W   0x0   Bit 26 to bit 16 of ARAM
              high-word                 ending address
              ACEAL: Accelerator aram Ending Address
                      Low DSP Address:0xFFD7
    15 . . . 0 Ending address R/W   0x0   Bit 15 to bit 0 of ARAM
              low-word                  ending address
             ACSAH: Accelerator aram Starting Address
                     High DSP Address:0xFFD4
    15 . . . 11               R     0x0   Reserved
    10 . . . 0 Starting      R/W   0x0   Bit 26 to bit 16 of ARAM
              address                   starting address
              high-word
             ACSAL: Accelerator aram Starting Address
                      Low DSP Address:0xFFD5
    15 . . . 0 Starting      R/W   0x0   Bit 15 to bit 0 of ARAM
              address                   starting address
              low-word